1. Field of the Invention
The present invention relates to a CMOS (complementary metal oxide semiconductor) transistor circuit, and more particularly, it relates to improvement in the operation characteristic of an OR-type ROM circuit formed of CMOS transistors.
2. Description of the Prior Art
FIG. 1 shows an example of a conventional OR-type ROM circuit which is formed by CMOS transistors. Referring to FIG. 1, the conventional OR-type ROM circuit includes n-channel MOS transistors T.sub.1 to T.sub.n for receiving address signals from address decoder circuits D.sub.1 to D.sub.n at respective gates thereof through respective word lines x.sub.1 to x.sub.n. The drains of the n-channel MOS transistors T.sub.1 to T.sub.n are commonly connected with each other while the respective sources thereof are connected to ground potentials G.
Provided between a signal line to which the drains of the n-channel MOS transistors T.sub.1 to T.sub.n are commonly connected and a power supply V is a p-channel MOS transistor PT.sub.1 which receives clock signals .phi. at its gate to be turned on/off for precharging a node B. Between the node B and an output terminal, provided are an inverter I for amplification which receives the signal level of the node B, and a p-channel MOS transistor PT.sub.2 for stabilizing the potential of the node B, and for ensuring high speed operation of the V.sub.OUT. The drain of the p-channel MOS transistor PT.sub.2 is connected to the node B and the source thereof is connected to the power supply V, while its gate receives output signals from the inverter I.
The address decoder circuits D.sub.1 to D.sub.n are respectively formed of AND-type decoder circuits. Namely, each of the address decoder circuits D.sub.1 to D.sub.n includes n-channel MOS transistors DN.sub.2 to DN.sub.y for receiving address signals AD.sub.i (i=2.about.y) at the gates thereof and an n-channel MOS transistor DN.sub.1 for receiving the clock signal .phi. at its gate. The source and drain terminals of the n-channel MOS transistors DN.sub.1 to DN.sub.y are alternately connected with each other while the source terminal of the n-channel MOS transistor DN.sub.1 is connected to the ground potential G to form an AND-type domino circuit. Provided between the drain of the n-channel MOS transistor DN.sub.2 and the power supply V is a p-channel MOS transistor DP.sub.1 for receiving the clock signal .phi. at its gate. Signals from the junction of the n-channel MOS transistor DN.sub.2 and the p-channel MOS transistor DP.sub.1 are outputted through an inverter DI onto a signal line (word line) x.sub.i to be an address decoded signal. Between the input portion of the inverter DI and the power supply V, provided is a p-channel MOS transistor DP.sub.2 which receives output signals from the inverter DI at its gate for ensuring high-speed operation of the decoder.
In the circuit configuration as shown in FIG. 1, address signals are supplied at each gate of the n-channel MOS transistors DN.sub.2 to DN.sub.y in the address decoder circuits D.sub.1 to D.sub.n to be decoded therein so that output signals V.sub.OUT of the inverter I are to be output signals from the ROM circuit for selecting, e.g., a word line selected by address signals.
FIG. 2 is a timing chart showing the operational timing of the circuit as shown in FIG. 1. With reference to FIGS. 1 and 2, the operation of this circuit is now described.
During a period T.sub.1 when the clock signals .phi. are at "L" levels, the p-channel MOS transistors DP.sub.1 and PT.sub.1, which receive the clock signals .phi. at the gates thereof, enter ON states. The clock signals .phi. are also supplied to the gate of the n-channel MOS transistor DN.sub.1 in each of the decoder circuits D.sub.1 to D.sub.n, and hence, at this time, the n-channel MOS transistor DN.sub.1 enters an OFF state and the potential of the junction of the p-channel transistor DP.sub.1 and the n-channel MOS transistor DN.sub.2 is turned into an "H" level. Therefore, "L" level signals are supplied onto the signal line x.sub.i (i=1 to n) through the inverter DI, which receives the said "H" signals. All of the n-channel MOS transistors T.sub.1 to T.sub.n, which receive the signals from the decoder circuits D.sub.1 to D.sub.n at the gates thereof, enter OFF states while the node B is precharged to an "H" level potential by voltage from the power supply V through the p-channel MOS transistor PT.sub.1, which is in turn in an ON state. The potential of the node B is supplied to the inverter I, whereby the level of the output V.sub.OUT is turned to an "L" level.
Then, during a period T.sub.2 when the clock signal .phi. is at an "H" level, both of the p-channel MOS transistors DP.sub.1 and PT.sub.1 enter OFF states while the n-channel MOS transistor DN.sub.1 enters an ON state. The n-channel MOS transistors DN.sub.2 to DN.sub.y of the respective decoder circuits D.sub.1 to D.sub.n are supplied with the address signals AD.sub.i at the gates thereof, whereby signals corresponding to the address signals AD.sub.i appear on the signal lines x.sub.1 to x.sub.n from the address decoder circuits D.sub.1 to D.sub.n. The decoder circuits D.sub.1 to D.sub.n receive addresses in different combinations such that the decoder circuit D.sub.1 receives AD.sub.1, AD.sub.2 and AD.sub.3, the decoder circuit D.sub.2 receives AD.sub.1, AD.sub.2 and AD.sub.3, . . . , in case of three-bit addresses, for example. Therefore, when all of the received address signals AD.sub.i are at "H" levels, the decoder circuit outputs "H" signals while outputting "L" signals when at least one of the received address signals AD.sub.i is at an "L" level, since the input portion of the inverter DI is precharged at an "H" level. The respective gates of the n-channel MOS transistors T.sub.1 to T.sub.n are supplied with the signals from the address decoder circuits D.sub.1 to D.sub.n, so that the respective n-channel MOS transistors T.sub.1 to T.sub.n are turned on/off in response to the address decode signals as received. The p-channel MOS transistor PT.sub.1 for receiving the clock signals .phi. in its gate is in an OFF state at this time, and hence, when an n-channel MOS transistor T.alpha. for receiving "H" signals at its gate enters an ON state, the potential of the node B is discharged through the n-channel MOS transistor T.alpha. which is in the ON state, to be turned to an "L" level. Thus, the output V.sub.OUT from the inverter I is turned on an "H" level.
When the clock signal .phi. is again turned to "L" level, similar operation is repeated to precharge the node B up to "H" level. At this time, the p-channel MOS transistor DP.sub.2 included in each of the address decoder circuits D.sub.1 to D.sub.n receives the output from the inverter DI and operates at a high speed to change the potential of the input part of the inverter DI at a high speed, thereby to decrease the through-current from the power supply to the ground potential at the inverter DI.
Then, during a period T.sub.3 when the clock signal .phi. is at "H" level, the node B is held at an "H" level of the precharge level and the output V.sub.OUT is maintained at an "L" level when no address is selected and all of the outputs from the decoder circuits D.sub.1 to D.sub.n are at "L" levels.
In the conventional OR-type ROM circuit as shown in FIG. 1, the clock signals .phi. are changed from "H" to "L" levels to precharge the potential of the node B from the "L" level to the "H" level through only one p-channel MOS transistor PT.sub.1. Therefore, a considerable long time is required to stabilize the potential of the node B at the "H" level, whereby the through-current from the power supply to the ground potential in the inverter I is increased followed by increase in power dissipation, while response operation of the outputs from the inverter I is retarded.
In proportion to increase in number of the n-channel MOS transistors T.sub.1 to T.sub.n, stray capacitance in the signal lines and parasitic capacitance of the MOS transistors or the like are increased to enlarge the aforementioned disadvantages.
An AND-connected CMOS logic circuit is disclosed in "Introduction to MOS LSI Design" by J. Mavor et al., published by University of Edinburgh and translated into Japanese by T. Sugano and published by Sangyo Tosyo Co. Ltd., April 1984, pp. 124-125. However, the aforementioned problems are not particularly caused in the AND-connected CMOS logic circuit.